On-chip testing circuit and method for integrated circuits

ABSTRACT

An integrated circuit includes an embedded memory device and an on-chip test circuit. The on-chip test circuit includes a multiplexer and one or more I/O circuits. The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device. As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry. This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit.

TECHNICAL FIELD

[0001] The present invention relates generally to testing of integratedcircuits, and more specifically to a method and apparatus that permitsaccessing of memory arrays embedded in the integrated circuitsindependent of any embedded logic arrays associated with the integratedcircuits.

BACKGROUND OF THE INVENTION

[0002]FIG. 1 is a simplified block diagram of an integrated circuit 10according to the prior art. The integrated circuit 10 includes anembedded memory device 12, also known as a matrix memory device 12,together with spare or redundant memory cells 12′. The embedded memorydevice 12 is coupled through an internal bus 14 to an embedded logicarray 16 that is also coupled to I/O circuitry 18 dedicated to theembedded logic array 16. As used herein, the term “embedded,” as appliedto circuitry contained on the integrated circuit 10, refers to a circuithaving one or more associated busses that are not normally directlyaccessible from outside of the integrated circuit 10.

[0003] In operation, the I/O circuitry 18 couples control and datasignals from external circuitry (not illustrated) to the embedded logicarray 16. The embedded logic array 16 operates on the data signals inaccordance with the control signals and generates intermediate or finalresults. These results are coupled from the embedded logic array 16through the internal bus 14 and are stored in the embedded memory device12. The embedded logic array 16 recalls these results at a later timeand uses them to generate output signals that are then coupled from theintegrated circuit 10 to the external circuitry through the embeddedlogic array 16 and the I/O circuitry 18. While the above-describedarrangement provides great advantages in achieving high data transferrates between the memory device 12 and the logic circuitry 16, it onlypermits the embedded memory device 12 to be externally accessed throughthe embedded logic array 16. In other words, unless the embedded logicarray 16 is operational, the embedded memory device 12 cannot be easilyaccessed for purposes such as testing. Further, the embedded memorydevice 12 may only be tested with those tests that are pre-programmedinto the embedded logic array 16 or through the I/O circuitry 18 of theembedded logic array 16.

[0004] The internal bus 14 includes ‘N’ data lines, where N may belarge, e.g., the internal bus 14 may be 64, 128, 256 or 512 bits wide ormay be even wider. When the internal bus 14 is wide or very wide, it isimpractical to provide I/O pads dedicated to each bit or data line ofthe internal bus 14. Furthermore, if the I/O pads 24 are to be connectedto externally accessible terminals, then buffers, electrostaticdischarge protection and other circuitry (not illustrated) must beprovided for each data line of the internal bus 14. Yet this additionalcircuitry for each data line would consume unacceptably large portionsof the integrated circuit 10 in order to provide external access to allof the data lines of the internal bus 14.

[0005] In many applications, the embedded memory device 12 is formedprior to forming the embedded logic array 16 for several differentreasons. Many memory circuits, such as the embedded memory device 12,require smaller linewidths (i.e., minimum feature sizes) than arenecessary for the embedded logic array 16, in order for the embeddedmemory device 12 to provide data storage densities consistent witheconomical fabrication of the integrated circuit 10. Also, theprocessing steps required to fabricate the embedded memory device 12 maybe different than those required to fabricate the embedded logic array16. These reasons, particularly in combination, often favor fabricatingthe embedded memory device 12 prior to fabricating the embedded logicarray 16.

[0006] A typical embedded memory device 12 in an integrated circuit 10includes at least one array of memory cells (not illustrated) arrangedin rows and columns. Each memory cell must be tested to ensure that itis operating properly. In a typical prior art test method, data having afirst binary value (e.g., a “1”) are written to and read from all memorycells in the arrays, and thereafter data having a second binary value(e.g., a “0”) are typically written to and read from the memory cells.The data written to the memory cells are known as “write” data, and thedata read from the memory cells are known as “read” data. The read dataare compared to a corresponding set of expect data. The expect datacorrespond to read data that would be provided by the integrated circuit10 if its embedded memory device 12 was operating properly. A memorycell is considered to be defective when the read data and thecorresponding expect data do not agree. As understood by one skilled inthe art, other test data patterns may be utilized in testing the memorycells, such as an alternating bit pattern, e.g., 101010 . . . , writtento the memory cells in each row of the memory device 12.

[0007] Defective memory cells that are identified by testing arereplaced with non-defective memory cells from rows or columns of spareor redundant memory cells 12′. In one conventional method for replacingdefective memory cells, fuses on the integrated circuit 10 are blown ina pattern corresponding to the addresses of defective memory cells. Thepattern is then compared to incoming addresses to select the rows orcolumns of redundant memory cells 12′ to replace rows or columns in thememory device 12 containing the defective memory cells.

[0008] However, it is desirable to be able to test the embedded memorydevice 12 before the embedded logic array 16 has been formed. Whenfabrication yields for the embedded memory device 12 are poor, or whenfabrication yields decrease, it may be undesirable to fabricate theembedded logic array 16 and combine it with the memory device 12 priorto testing the memory device 12. Further, discovering fabricationproblems early in forming the integrated circuit 10 allows correctivesteps to be taken early, reducing the number of integrated circuits 10affected by a particular fabrication problem. Early detection offabrication problems favors increased yields and reduced waste.

[0009] Accordingly, there is a need for an on-chip test circuit topermit testing of embedded memory devices in integrated circuits priorto fabrication of dedicated logic circuits for the integrated circuits.

SUMMARY OF THE INVENTION

[0010] In one aspect of the present invention, an integrated circuitincludes an embedded memory device coupled to an internal bus having afirst number of data lines, a multiplexer and an I/O port having asecond number of data lines that is less than the first number of datalines. The multiplexer allows the I/O port to be coupled to a portion ofthe data lines of the internal bus and thus to at least a portion of theembedded memory device. As a result, the embedded memory device may betested or repaired before an embedded logic function associated withdedicated I/O pins or pads is added to the integrated circuit. Thispromotes improved economic efficiency by allowing a manufacturer to cullintegrated circuits that do not have acceptable fabrication yields priorto fabrication of the embedded logic array.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a simplified block diagram of an integrated circuitaccording to the prior art.

[0012]FIG. 2 is a simplified block diagram of an integrated circuitincluding an on-chip testing circuit in accordance with an embodiment ofthe present invention.

[0013]FIG. 3 is a flow chart of a process for forming the integratedcircuit of FIG. 2 in accordance with an embodiment of the presentinvention.

[0014]FIG. 4 is a simplified block diagram of a computer systemincluding the integrated circuit of FIG. 2 in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0015]FIG. 2 is a simplified block diagram of an integrated circuit 20including an on-chip testing circuit 22 in accordance with an embodimentof the present invention. The integrated circuit 20 includes theembedded memory device 12 coupled to the on-chip testing circuit 22 andmay include the embedded logic array 16 as described above inassociation with FIG. 1. In one embodiment, the embedded memory device12 includes a memory circuit such as a dynamic random access memory(“DRAM”). The on-chip testing circuit 22 includes I/O pins or pads 24and a multiplexer (“MUX”) 26. The on-chip testing circuit 22 includes abus 27 that couples a bi-directional buffer 28 to a first set of dataports of the MUX 26 and to the I/O pins or pads 24.

[0016] In one embodiment, the I/O pads 24 are shared by the testingcircuit 22 and the I/O circuitry 18, i.e., the I/O pads 24 are a subsetof the I/O circuitry 18. As a result, the same I/O pads 24 and/or pinscan be used for testing and for normal operations.

[0017] The I/O pins or pads 24, the bus 27, the bi-directional buffer 28and the first set of data ports of the MUX 26 each include ‘M’ digitaldata lines, which is substantially fewer than the ‘N’ data lines of theinternal bus 14. In one embodiment, M may be related to N as inM=N/2^(n). For example, M might be 16 while N might be 512, i.e.,n=five, however, M may be any number greater than or equal to one, buttypically will be less than thirty-two. The on-chip test circuit 22 alsoincludes a test mode logic circuit 30 having inputs coupled to the I/Ocircuitry 18 and having outputs coupled to the MUX 26. The test modelogic circuit 30 provides control signals to the MUX 26 to select asubset of the N data lines of the internal data bus 14 to be coupled tothe M I/O pins or pads 24. In one embodiment, a subset of M of N seconddata ports of the MUX 26 is coupled to a corresponding subset of M ofthe N data lines of the internal bus 14. In another embodiment, a subsetof M data ports of the MUX 26 is coupled to a multiple of M of the Ndata lines of the internal bus 14 through optional compression circuitry32.

[0018] In some applications, the I/O pins or pads 24 are accessedthrough probes by an automated tester 34 prior to completion ofpackaging of the integrated circuit 20, allowing testing of the embeddedmemory device 12 while the integrated circuit 20 is still in wafer form.The embedded memory device 12 may be repaired, as discussed above, andthe repair of the embedded memory device 12 may precede fabrication ofthe embedded logic array 16. In other embodiments, the I/O pins or pads24 may be bonded to pins in the completed, packaged integrated circuit20, providing external access to the embedded memory device 12 even inthe event that the embedded logic array 16 is not functional. Bondingthe I/O pads 24 to package pins also permits a broader range of teststhan those tests that are pre-programmed into the embedded logic array16 to be applied to the embedded memory device 12.

[0019]FIG. 3 is a flow chart of a process 40 for forming the integratedcircuit 20 of FIG. 2 according to an embodiment of the presentinvention. The process 40 begins after the embedded memory device 12 hasalready been formed. In a step 42, a test port on a tester, such as theautomated tester 34, is coupled to the I/O pads 24. In one embodiment, aprobe card having a number of probes is used to make temporaryconnections to the I/O pads 24. Any other temporary connections (powersupply, control signals for the MUX 26 etc.) required to be able to testthe embedded memory device 12 are also made to the integrated circuit20. In a step 44, a group of index variables m are selected thatcorrespond to addresses for a first group of rows (0:N/2^(n)−1) thatform a portion of the embedded memory device 12 selected for testing. Ina step 46, the MUX 26 is programmed to couple the selected rows to theI/O pads 24. In a step 48, background data are supplied to the selectedrows of the embedded memory device 12. In a step 50, read data areextracted from the selected portion of the embedded memory device 12through the I/O pads 24. In a query task 52, the automated tester 34determines if the read data and the corresponding expect data agree.

[0020] When the query task 52 determines that the read data and thecorresponding expect data do not agree, data describing the failedmemory cell (e.g., the cell address) are written to a memory in theautomated tester in a step 54. When the query task 52 determines thatthe read data and the corresponding expect data do agree, control passesto a query task 56.

[0021] The query task 56 determines if all of the columns in theembedded memory device 12 have been tested. When the query task 56determines that not all of the columns in the embedded memory device 12have been tested, control passes to a step 58. In the step 58, a columncounter is incremented and control then returns to the step 48. When thequery task 56 determines that all of the columns in the embedded memorydevice 12 have been tested, control passes to a query task 60.

[0022] The query task 60 determines if all of the rows in the embeddedmemory device 12 have been tested. When not all of the rows in theembedded memory device 12 have been tested, control passes to a step 62.In the step 62, the control signals to the MUX 26 are incremented. Inone embodiment, the control signals to the MUX 26 are incremented totest the rows adjacent to the rows that have just been tested. SinceM=N/2^(n), the index variables m corresponding to the rows beingaddressed are incremented by N/2^(n) in this embodiment. When all of therows in the embedded memory device 12 have been tested, control passesto a step 64.

[0023] In the step 64, the embedded memory device 12 is repaired. In oneembodiment, the defective memory cells in the embedded memory device 12are replaced in a conventional manner by blowing fuses or antifuses in apattern corresponding to addresses of rows or columns including thedefective memory cells that were identified in the query task 52.Antifuses are devices that are initially nonconductive but which may bestressed or “blown” by an appropriate bias to become permanentlyconductive.

[0024] In a step 66, the embedded logic array 16 and the remainder ofthe integrated circuit 20 are formed through conventional fabricationprocedures. The process 40 then ends.

[0025] In a different embodiment of the process 40, some datacompression is employed in testing the embedded memory device 12. Forexample, in the step 46, not only are M many rows selected by the MUX26, but an additional group of rows is also selected by the optionalcompression circuitry 32. The additional group of rows might include,e.g., another M many rows, or it might include, e.g., another 3M manyrows. In the step 48, background data are supplied to all of theselected rows via the optional compression circuitry 32. In the step 50,combinatorial logic in the optional compression circuitry 32 combinesthe read data from all of the selected rows such that the query task 52is able to determine that one of the several rows corresponding to oneof the M I/O pads 24 includes a defective memory cell. In oneembodiment, the several rows associated with the I/O pad 24 carrying thedata indicative of a memory cell failure are replaced with a group ofrows from the redundant memory cells 12′ to repair the embedded memorydevice 12. This embodiment provides some speed advantages in testing ofthe embedded memory device 12.

[0026] It will be appreciated that variations in the process 40 arepossible. For example, the steps relating to rows could be stepsrelating to columns and vice versa.

[0027]FIG. 4 is a simplified block diagram of a portion of a computersystem 80 including the memory integrated circuit 20 of FIG. 2 inaccordance with an embodiment of the present invention. The computersystem 80 includes a central processing unit 82 for performing variouscomputing functions, such as executing specific software to performspecific calculations or tasks. The central processing unit 82 iscoupled via a bus 84 to a memory 86, a user input interface 88, such asa keyboard or a mouse, function circuitry 90 and a display 92. Thememory 86 may or may not include a memory management module (notillustrated). The memory 86 does include ROM for storing instructionsproviding an operating system and also includes read-write memory fortemporary storage of data. The processor 82 operates on data from thememory 86 in response to input data from the user input interface 88 anddisplays results on the display 92. The processor 82 also stores data inthe read-write portion of the memory 86.

[0028] The function circuitry 90 is an example where the integratedcircuit 20 of FIG. 2 may be particularly effective. For example, whenthe function circuitry 90 includes an encryption engine, a digitalsignal processing chip (e.g., video processor, vocoder, 3-dimensionalcomputer graphics, image processing or the like) or provides some otherdedicated or programmable complex function, as described, for example,in “An Access-Sequence Control Scheme to Enhance Random-AccessPerformance of Embedded DRAMs,” by K. Ayukawa et al., IEEE Journal ofSolid State Circuits 33(5):800-806, 1998, the integrated circuit 20 willinclude both read-write memory functions and logic functions, such asthose provided by the embedded memory device 12 and the embedded logicarray 16, respectively (see FIGS. 1 and 2). In turn, these functions maybe realized least expensively when the embedded memory device 12 can beevaluated prior to completing fabrication of the embedded logic array16.

[0029] Examples of systems where the computer system 80 findsapplication include personal/portable computers, camcorders,televisions, automobile electronic systems, microwave ovens and otherhome and industrial appliances.

[0030] It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. Therefore, the present invention is to be limited only by theappended claims.

1. An integrated circuit comprising: an internal bus having ‘N’ datalines; an embedded memory device coupled to the internal bus; amultiplexer having ‘N’ first data ports each coupled to a respective oneof the N data lines of the internal bus and ‘M’ second data ports, where‘M’ is less than ‘N’; a controller coupled to the multiplexer andselecting a subset of ‘M’ of the ‘N’ data lines in the internal bus tobe coupled to the ‘M’ second data ports of the multiplexer; and ‘M’ I/Oports each coupled to a respective one of the ‘M’ second data ports ofthe multiplexer.
 2. The integrated circuit of claim 1, furthercomprising data compression circuitry including ‘N’ data ports coupledto the ‘N’ data lines of the internal bus and ‘M’ data ports coupled tothe ‘M’ second data ports of the multiplexer.
 3. The integrated circuitof claim 1, further comprising: data compression circuitry including ‘N’data ports coupled to the ‘N’ data lines of the internal bus and ‘M’data ports coupled to the ‘M’ second data ports of the multiplexer; andan embedded logic array including ‘N’ data ports coupled to the ‘N’ datalines of the internal bus and a second set of ports coupled to dedicatedI/O ports, the embedded logic array having been formed on the integratedcircuit after functional testing of the embedded memory device.
 4. Theintegrated circuit of claim 1 wherein the embedded memory devicecomprises a random access memory device.
 5. The integrated circuit ofclaim 1 wherein ‘N’ is equal to a power of two times ‘M’.
 6. Theintegrated circuit of claim 1 wherein ‘M’ has a value from one to sixtyfour inclusive.
 7. The integrated circuit of claim 1 wherein ‘M’ is lessthan thirty two.
 8. The integrated circuit of claim 1, furthercomprising: a plurality of dedicated I/O ports; and an embedded logicarray including ‘N’ data ports each coupled to a respective one of the‘N’ data lines of the internal bus and including data and control signalports coupled to the plurality of dedicated I/O ports.
 9. The integratedcircuit of claim 8 wherein the embedded logic array was formed on theintegrated circuit after functional testing of the embedded memorydevice.
 10. The integrated circuit of claim 8 wherein the embedded logicarray was formed on the integrated circuit after repair of the embeddedmemory device.
 11. The integrated circuit of claim 8 wherein theembedded logic array was formed on the integrated circuit afterreplacement of portions of the embedded memory device with redundantmemory cells by blowing fuses in a pattern corresponding to a pattern ofdefective memory cells in the embedded memory device.
 12. The integratedcircuit of claim 1 wherein the embedded memory device comprises a randomaccess memory device including a matrix memory device and redundantmemory cells, defective memory cells of the matrix memory device havingbeen replaced by memory cells from the redundant memory cells by blowinga series of fuses.
 13. The integrated circuit of claim 12, furthercomprising an embedded logic array having ‘N’ data ports coupled to the‘N’ data lines of the internal bus and a second set of ports coupled todedicated I/O ports.
 14. The integrated circuit of claim 13 wherein theembedded logic array was formed on the integrated circuit afterfunctional testing of the embedded memory device and replacement of thedefective matrix memory cells by the redundant memory cells.
 15. Anintegrated circuit comprising: an internal bus having ‘N’ data lines; anembedded memory device coupled to the internal bus; a multiplexer having‘N’ first data ports each coupled to a respective one of the N datalines of the internal bus and ‘M’ second data ports, where ‘M’ is lessthan ‘N’; a controller coupled to the multiplexer and selecting a subsetof ‘M’ of the ‘N’ data lines in the internal bus to be coupled to the‘M’ second data ports of the multiplexer; ‘M’ I/O ports each coupled toa respective one of the ‘M’ second data ports of the multiplexer; and anembedded logic array including ‘N’ data ports coupled to the ‘N’ datalines of the internal bus and a second set of ports coupled to dedicatedI/O ports, the embedded logic array having been formed on the integratedcircuit after functional testing of the embedded memory device.
 16. Theintegrated circuit of claim 15, further comprising data compressioncircuitry including ‘N’ data ports coupled to the ‘N’ data lines of theinternal bus and ‘M’ data ports coupled to the ‘M’ second data ports ofthe multiplexer.
 17. The integrated circuit of claim 15 wherein theembedded memory device comprises a random access memory device.
 18. Theintegrated circuit of claim 15 wherein ‘N’ is equal to a power of twotimes ‘M’.
 19. The integrated circuit of claim 15 wherein ‘M’ has avalue from one to sixty four inclusive.
 20. The integrated circuit ofclaim 15, further comprising: a plurality of dedicated I/O ports; and anembedded logic array including ‘N’ data ports each coupled to arespective one of the ‘N’ data lines of the internal bus and includingdata and control signal ports coupled to the plurality of dedicated I/Oports.
 21. The integrated circuit of claim 20 wherein the embedded logicarray was formed on the integrated circuit after functional testing ofthe embedded memory device.
 22. The integrated circuit of claim 20wherein the embedded logic array was formed on the integrated circuitafter repair of the embedded memory device.
 23. The integrated circuitof claim 20 wherein the embedded logic array was formed on theintegrated circuit after replacement of portions of the embedded memorydevice with redundant memory cells by blowing fuses in a patterncorresponding to a pattern of defective memory cells in the embeddedmemory device.
 24. The integrated circuit of claim 15 wherein theembedded memory device comprises a random access memory device includinga matrix memory device and redundant memory cells, defective memorycells of the matrix memory device having been replaced by memory cellsfrom the redundant memory cells by blowing a series of fuses.
 25. Theintegrated circuit of claim 24, further comprising an embedded logicarray having ‘N’ data ports coupled to the ‘N’ data lines of theinternal bus and a second set of ports coupled to dedicated I/O ports.26. An integrated circuit comprising: an embedded memory device having‘N’ data bus terminals; a multiplexer having ‘N’ first data ports eachcoupled to a respective one of the ‘N’ data bus terminals and ‘M’ seconddata ports, where ‘M’ is less than ‘N’; and ‘M’ I/O ports each coupledto a respective one of the second data ports.
 27. The integrated circuitof claim 26 wherein the data bus terminals are each coupled to arespective one of ‘N’ columns of memory cells in the memory device. 28.The integrated circuit of claim 26, further comprising a controllercoupled to the multiplexer and selecting a subset of ‘M’ of the ‘N’ databus terminals to be coupled to the “M” second data ports in response toexternally-supplied control signals.
 29. The integrated circuit of claim26 wherein ‘M’ is less than thirty two.
 30. The integrated circuit ofclaim 26, further comprising data compression circuitry including ‘N’ports coupled to the ‘N’ data bus terminals and ‘M’ ports coupled to thesecond data ports.
 31. The integrated circuit of claim 26 wherein theembedded memory device comprises a random access memory device includinga matrix memory device and redundant memory cells, defective memorycells of the matrix memory device having been replaced by memory cellsfrom the redundant memory cells by blowing a series of fuses in theintegrated circuit.
 32. The integrated circuit of claim 26, furthercomprising a logic array including ‘N’ ports coupled to the ‘N’ data busterminals and including a plurality of I/O ports coupled to acorresponding plurality of I/O pins.
 33. The integrated circuit of claim32 wherein the logic array was formed on the integrated circuit afterfunctional testing of the embedded memory device.
 34. The integratedcircuit of claim 32 wherein the logic array was formed on the integratedcircuit after functional testing of the embedded memory device andreplacement of defective memory cells with redundant memory cells. 35.An integrated circuit comprising: an internal bus having a first datawidth; an embedded matrix memory device coupled to the internal bus; anembedded logic array coupled to the internal bus; a first set of I/Oports coupled to the embedded logic array; a multiplexer including afirst set of data ports having the first data width coupled to theinternal bus and having a second set of data ports having a second datawidth that is less than the first data width; and a second set of I/Oports having the second data width, the second set of ports coupled tothe second set of multiplexer data ports.
 36. The integrated circuit ofclaim 35 wherein the multiplexer further comprises a data compressioncircuit coupled between the second set of multiplexer data ports and theinternal bus.
 37. The integrated circuit of claim 35 wherein the firstdata width is greater than sixty-four bits.
 38. The integrated circuitof claim 35, further comprising redundant memory cells coupled to theembedded matrix memory device, defective memory cells of the embeddedmatrix memory device having been replaced by redundant memory cells. 39.The integrated circuit of claim 35 wherein the embedded logic array wasformed after functional testing of the embedded matrix memory device.40. The integrated circuit of claim 35 wherein at least some of the I/Oports in the first set comprise I/O ports in the second set of I/Oports.
 41. A computer comprising: a data and address bus; a centralprocessing unit coupled to the data and address bus; an input devicecoupled to data and address bus; a display coupled to the data andaddress bus; a memory coupled to the central processing unit, the memoryincluding a ROM storing instructions providing an operating system forthe central processing unit and including a read-write memory providingtemporary storage of data; and a function circuit coupled to the dataand address bus, the function circuit comprising: an embedded memorydevice having ‘N’ data bus terminals; a multiplexer including ‘N’ firstdata ports each coupled to a respective one of the ‘N’ data busterminals and including ‘M’ second data ports, where ‘M’ is less than‘N’; ‘M’ I/O ports each coupled to a respective one of the ‘M’multiplexer second data ports; and an embedded logic array including ‘N’data ports coupled to the ‘N’ data bus terminals and also including I/Oports coupled to I/O pins.
 42. The computer of claim 41 wherein theembedded logic array was formed on the integrated circuit afterfunctional testing of the embedded memory device.
 43. The computer ofclaim 41 wherein the function circuit comprises a graphics and imageprocessor.
 44. the computer of claim 42 wherein in the function circuitat least some of the I/O ports in the first set comprise I/O ports inthe second set of I/O ports.
 45. A method of making an integratedcircuit including an embedded memory device, the method comprising:forming the embedded memory device, redundant memory cells and amultiplexer on the integrated circuit, forming a multiplexer on theintegrated circuit the multiplexer including ‘N’ data ports coupled to‘N’ data bus terminals of the embedded memory device and ‘M’ data portscoupled to ‘M’ I/O ports, where ‘M’ is less than ‘N’; testing theembedded memory device by coupling test signals into and out of theembedded memory device through the multiplexer and ‘M’ I/O ports todetermine if there are any defective memory cells in the embedded memorydevice; replacing defective memory cells in the embedded memory devicewith redundant memory cells; and forming an embedded logic array having‘N’ data ports coupled to the ‘N’ data bus terminals of the embeddedmemory device, the embedded logic array including I/O ports coupled topins of the integrated circuit.
 46. The method of claim 44 whereinreplacing defective memory cells precedes forming an embedded logicarray.
 47. The method of claim 44 wherein replacing defective memorycells comprises replacing defective memory cells with redundant memorycells by blowing fuses on the integrated circuit in a patterncorresponding to a pattern of addresses of defective embedded memorydevice cells.
 48. The method of claim 44 wherein testing the embeddedmemory device comprises: coupling temporary interconnections to the ‘M’I/O ports; supplying address data to the multiplexer; supplyingbackground data to the embedded memory device through the temporaryinterconnections and the multiplexer; reading read data from theembedded memory device through the temporary interconnections and themultiplexer; comparing the read data to corresponding expect data; and,when the read data do not agree with the corresponding expect data:recording an address for a defective embedded memory device memory cell.49. The method of claim 48 wherein coupling temporary interconnectionsto the ‘M’ I/O ports comprises coupling wafer probe pins to the ‘M’ I/Oports.
 50. The method of claim 44 wherein testing the embedded memorydevice comprises: coupling temporary interconnections to the ‘M’ I/Oports; coupling a group of ‘M’ of the ‘N’ data bus terminals of theembedded memory device to the temporary interconnections; testing thegroup of ‘M’ data bus terminals of the embedded memory; coupling a groupof ‘M’ data bus terminals adjacent the group of ‘M’ data bus terminalsthat were tested to the temporary interconnections; and testing thegroup of ‘M’ data bus terminals of the embedded memory adjacent thegroup of ‘M’ data bus terminals that were tested.
 51. The method ofclaim 50, further comprising iterating coupling a group of ‘M’ rowsadjacent the group of ‘M’ rows that were tested to the temporaryinterconnections and testing the group of ‘M’ rows of the embeddedmemory adjacent the group of ‘M’ rows that were tested until all ‘N’rows of the embedded memory have been tested.
 52. A method of forming anembedded logic array on an integrated circuit comprising: coupling agroup of temporary interconnections to ‘M’ I/O pads; coupling controlsignals to a multiplexer, the control signals causing the multiplexer todirect which of ‘N’ rows of an embedded memory device are coupled to the‘M’ I/O pads, where ‘M’ is less than ‘N’; testing memory cells in theembedded memory device with signals coupled to the embedded memorydevice through the temporary interconnections and the multiplexer, and,when a memory cell fails, writing an address corresponding to the failedmemory cell to a memory contained in an automated tester; and formingthe embedded logic array having ‘N’ data ports coupled to the ‘N’ rowsof the embedded memory device, the embedded logic array including I/Oports coupled to at least some of the I/O pads of the integratedcircuit.
 53. The method of claim 52 wherein testing memory cellscomprises: supplying background data to the embedded memory devicethrough the temporary interconnections; extracting read data from theembedded memory device in response to the background data; and comparingthe read data to corresponding expect data; and, when the read data donot agree with the corresponding expect data, identifying a memory cellproviding the read data that do not agree with the corresponding expectdata as a failed memory cell.
 54. The method of claim 52, furthercomprising replacing failed memory cells in the embedded memory devicewith redundant memory cells on the integrated circuit.
 55. The method ofclaim 54 wherein replacing failed memory cells comprises blowing fuseson the integrated circuit in a pattern corresponding to a pattern offailed memory cells in the embedded memory device.
 56. The method ofclaim 52 wherein coupling a group of temporary interconnections to agroup of ‘M’ I/O pads comprises coupling wafer probe pins to the groupof ‘M’ I/O pads.
 57. A method of forming an integrated circuitcomprising: coupling a group of temporary interconnections to ‘M’ I/Opads; coupling control signals to a multiplexer and data compressor onthe integrated circuit, the control signals directing a multiple of ‘M’of ‘N’ rows of a memory device to couple to the ‘M’ I/O pads, where ‘M’is less than ‘N’; supplying background data to the memory device throughthe temporary interconnections; extracting read data from the memorydevice in response to the background data; comparing the read data tocorresponding expect data; and, when the read data do not agree with thecorresponding expect data, writing failure data to a memory contained inan automated tester, the failure data including address informationidentifying a group of rows or columns of memory cells including thememory cell providing the read data that do not agree with thecorresponding expect data; and forming the embedded logic arrayincluding ‘N’ data ports coupled to the ‘N’ rows of the embedded memorydevice, the embedded logic array including I/O ports coupled to pins ofthe integrated circuit.
 58. The method of claim 57, further comprisingreplacing rows or columns of memory cells in the embedded memory devicethat include memory cells providing read data that do not agree withcorresponding expect data with rows or columns of redundant memorycells.
 59. The method of claim 58 wherein forming an embedded logicarray occurs after replacing rows or columns of memory cells in theembedded memory device.